Recently, synchronous memory devices that operate synchronized with a clock signal are widely used as main memory devices in personal computers and the like. Among them, a DDR (Double Data Rate) synchronous memory device requires input and output data being accurately synchronized with an external clock signal. Therefore, a DDL circuit for generating an internal clock signal that is synchronized with an external clock signal is necessary (see Japanese Patent Application Laid-open No. 2002-324398).
A single-phase DLL circuit commonly used is shown in FIG. 7.
As shown in FIG. 7, the single-phase DLL circuit has a delay adjusting circuit unit 10 that adjusts an amount of delay of an external clock signal CK, and a clock driver unit 20 that receives an internal clock signal LCLK outputted from the delay adjusting circuit unit 10. The clock driver unit 20 includes clock drivers 21 that supplies the internal clock signal LCLK to a real path 31 in a clock tree unit 30, and clock drivers 22 that supplies the internal clock signal LCLK to a replica path 32 in the clock tree unit 30.
The internal clock signal LCLK passed through the real path 31 is supplied to an output buffer 41 in a buffer circuit unit 40. The output buffer 41 is a circuit that outputs read data DRFIFO to an input/output data terminal DQ synchronized with the internal clock signal LCLK. The internal clock signal LCLK passed through the replica path 32 is supplied to a replica buffer 42. The replica buffer 42 is a circuit that outputs a replica clock signal RCLK synchronized with the internal clock signal LCLK.
The replica clock signal RCLK outputted from the replica buffer 42 is fed back to the delay adjusting circuit unit 10. The delay adjusting circuit unit 10 is configured by a phase detecting circuit 11 and a delay adjusting circuit 12. The replica clock signal RCLK is supplied to an inverting input terminal (−) of the phase detecting circuit 11. The external clock signal CK is supplied to a non-inverting input terminal (+) of the phase detecting circuit 11.
Accordingly, a feedback signal FB corresponding to a difference between an edge of the replica clock signal RCLK and an edge of the external clock signal CK is generated and supplied to the delay adjusting circuit 12. The delay adjusting circuit 12 adjusts an amount of delay of the internal clock signal LCLK based on the feedback signal FB so as to align the edge of the replica clock signal RCLK with the edge of the external clock signal CK.
The clock drivers 22 include a dividing circuit 51 and a delay adjusting circuit 52. The dividing circuit 51 is installed to frequency-divide the internal clock signal LCLK passing through the replica path 32 thereby to reduce power consumption. The delay adjusting circuit 52 is a circuit for canceling a difference between the read data appearing at the input/output data terminal DQ and the replica clock signal RCLK. That is, the output buffer 41 and the replica buffer 42 have a difference in the operation speeds resulting from a difference in the output loads, as well as a difference in the amounts of delay due to a dead zone of the phase detecting circuit 11. The delay adjusting circuit 52 is installed to cancel a difference in timing caused by these differences.
The single-phase DLL circuit is advantageous in that the circuit configuration is relatively simple. However, the single-phase DLL circuit has a disadvantage of not operating correctly when the frequency of the external clock signal CK is high, because the delay adjusting circuit unit 10 cannot keep up with the clock signal.
Such a problem can be solved by using a multiphase DLL circuit. A multiphase DLL circuit adjusts an amount of delay of the internal clock signal LCLK not by using the external clock signal CK as it is, but controls an amount of delay referring to a frequency-divided signal that is obtained by dividing the external clock signal CK. Accordingly, the delay adjusting circuit unit assures a sufficient operation speed, and thus it can operate correctly even when the frequency of the external cock CK is high.
In the multiphase DLL circuit, however, skew increases or duty varies easily when the power supply voltage fluctuates. The main cause is considered as follows: The multiphase DLL circuit frequency-divides an external clock signal CK into plural frequency-divided signals, and control an amount of delay with respect to each of these frequency-divided signals. Therefore, when the power supply voltage fluctuates, the influences on the respective frequency-divided signals are not equal.